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(R)
X9251
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet April 13, 2007 FN8166.5
Quad Digitally-Controlled (XDCPTM) Potentiometer
The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple-mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Four potentiometers in one package * 256 resistor taps-0.4% resolution * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper resistance: 100 typical @ VCC = 5V * 4 Non-volatile data registers for each potentiometer * Non-volatile storage of multiple wiper positions * Standby current <5A max * VCC: 2.7V to 5.5V Operation * 50k, 100k versions of total resistance * 100 year data retention * Single supply version of X9250 * Endurance: 100,000 data changes per bit per register * 24 Ld SOIC, 24 Ld TSSOP * Low power CMOS * Pb-free plus anneal available (RoHS compliant)
Functional Diagram
VCC RH0 RH1 RH2 RH3
HOLD A1 A0 SO SI SCK CS SPI Interface WCR0 DR00 DR01 DR02 DR03
DCP0
POWER UP, INTERFACE CONTROL AND STATUS
WCR1 DR10 DR11 DR12 DR13
DCP1
WCR2 DR20 DR21 DR22 DR23
DCP2
WCR3 DR30 DR31 DR32 DR33
DCP3
VSS
WP
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9251 Ordering Information
PART NUMBER X9251US24 X9251US24Z (Note) X9251UV24 X9251UV24Z (Note) X9251TS24 X9251TS24Z (Note) X9251TS24I X9251TS24IZ (Note) X9251TV24I X9251TV24IZ (Note) X9251US24I-2.7 PART MARKING X9251US X9251US Z X9251UV X9251UV Z X9251TS X9251TS Z X9251TS I X9251TS ZI X9251TV I X9251TV ZI X9251US G 2.7 to 5.5 50 100 VCC LIMITS (V) 5 10% POTENTIOMENTER ORGANIZATION TEMP RANGE (k) (C) 50 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 100 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 PACKAGE 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) PKG. DWG. # M24.3 M24.3 MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) M24.3 M24.3 M24.3 M24.3 MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) M24.3 M24.3 MDP0044
X9251US24IZ-2.7 (Note) X9251US ZG X9251UV24-2.7 X9251UV24Z-2.7 (Note) X9251UV24I-2.7 X9251UV F X9251UV ZF X9251UV G
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24IZ-2.7 (Note) X9251UV ZG X9251TS24-2.7 X9251TS24Z-2.7 (Note) X9251TV24-2.7 X9251TV24Z-2.7 (Note) X9251TV24I-2.7 X9251TV24IZ-2.7 (Note) X9251TS F X9251TS ZF X9251TV F X9251TV ZF X9251TV G X9251TV ZG
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) M24.3 M24.3 MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 24 Ld TSSOP (4.4mm) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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X9251 Circuit Level Applications
* Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits
SO A0 RW3 RH3 RL3 NC VCC RL0 RH0 RW0 CS WP
Pinout
X9251 (24 LD SOIC/TSSOP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 X9251 24 23 22 21 20 19 18 17 16 15 14 13 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 A1 SI
Pin Assignments
PIN (SOIC) 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 6, 19 NOTE: 1. A0 and A1 device address pins must be tied to a logic level. SYMBOL SO A0 RW3 RH3 RL3 VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 VSS RW2 RH2 RL2 SCK HOLD NC FUNCTION Serial Data Output for SPI bus Device Address for SPI bus. (See Note 1) Wiper Terminal of DCP3 High Terminal of DCP3 Low Terminal of DCP3 System Supply Voltage Low Terminal of DCP0 High Terminal of DCP0 Wiper Terminal of DCP0 SPI bus. Chip Select active low input Hardware Write Protect - active low Serial Data Input for SPI bus Device Address for SPI bus. (See Note 1) Low Terminal of DCP1 High Terminal of DCP1 Wiper Terminal of DCP1 System Ground Wiper Terminal of DCP2 High Terminal of DCP2 Low Terminal of DCP2 Serial Clock for SPI bus Device select. Pauses the SPI serial bus. No Connect
System Level Applications
* Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems
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X9251 Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9251. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 AND A0) The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1 and A0 must be tied to a logic level which specifies the internal address of the device, see Figures 2, 3, 4, 5 and 6. CHIP SELECT (CS) When CS is HIGH, the X9251 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS LOW enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers.
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR).
Potentiometer Pins
RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminals of DCP0 and so on.
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X9251
One of Four Potentiometers
#: 0, 1, 2, or 3 SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#0 8 DR#1 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR#) SERIAL BUS INPUT RH
DR#2
DR#3
COUNTER --DECODE
DCP CORE
RW
IF WCR = 00[H] then RW is closet to RL IF WCR = FF[H] then RW is closet to RH
INC/DEC LOGIC UP/DN MODIFIED SCK UP/DN CLK RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW (i.e., VCC VH, VL, VW). The VCC ramp rate specification is always in effect.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a non-volatile operation and takes a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0 ~ 255).
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR#0) upon power-up. (See Figure 1) The wiper counter register is a volatile register; that is, its contents are lost when the X9251 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR#.
Status Register (SR)
This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. * When WIP = 1, indicates that high-voltage write cycle is in progress. * When WIP = 0, indicates that no high-voltage write cycle is in progress.
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X9251
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE) WCR7 (MSB) TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 (LSB)
Serial Interface
The X9251 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in, on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.
The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is the logic value at the input pin A1, and A0 is the logic value at the input pin A0. Only the device which Slave Address matches the incoming bits sent by the master executes the instruction. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
Instruction Byte
The next byte sent to the X9251 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs.The format is shown below in Table 4.
Identification Byte
The first byte sent to the X9251 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the Identification Byte are a Device Type Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT Device Type Identifier ID3 0 (MSB) TABLE 4. INSTRUCTION BYTE FORMAT Instruction Opcode I3 (MSB) I2 I1 I0 RB Register Selection RA DCP Selection (WCR Selection) ID2 1 ID1 0 ID0 1 A3 0 A2 0 Slave Address A1 Pin A1 Logic Value A0 Pin A0 Logic Value (LSB)
P1
P0 (LSB)
Data Register Selection
REGISTER DR#0 DR#1 DR#2 DR#3 #: 0, 1, 2, or 3 RB 0 0 1 1 RA 0 1 0 1
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X9251
TABLE 5. INSTRUCTION SET INSTRUCTION SET INSTRUCTION Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register NOTE: 1/0 = data is one or zero I3 1 1 1 1 1 I2 0 0 0 1 1 I1 0 1 1 0 0 I0 1 0 1 0 1 RB 0 0 1/0 1/0 1/0 RA 0 0 1/0 1/0 1/0 P1 1/0 1/0 1/0 1/0 1/0 P0 1/0 1/0 1/0 1/0 1/0 OPERATION Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Data Register pointed to by P1 - P0 and RB - RA Write new value to the Data Register pointed to by P1 - P0 and RB - RA Transfer the contents of the Data Register pointed to by P1 - P0 and RB - RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by RB - RA Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P1 - P0
1
1
1
0
1/0
1/0
1/0
1/0
0
0
0
1
1/0
1/0
0
0
1
0
0
0
1/0
1/0
0
0
0
0
1
0
0
0
1/0
1/0
Instructions
Four of the nine instructions are three bytes in length. These instructions are: * Read Wiper Counter Register - read the current wiper position of the selected potentiometer, * Write Wiper Counter Register - change current wiper position of the selected potentiometer, * Read Data Register - read the contents of the selected Data Register, * Write Data Register - write a new value to the selected Data Register, * Read Status - this command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometer's WCR, and one of its associated registers, 7
DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9251; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. * XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. * Global XFR Data Register to Wiper Counter Register - This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. * Global XFR Wiper Counter Register to Data Register - This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers.
FN8166.5 April 13, 2007
X9251 Increment/Decrement Command
The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9251 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one wiper position towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details.
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A1 A0 I3 I2 I1 I0 RB RA P1 P0
DEVICE ID
INTERNAL ADDRESS
INSTRUCTION OPCODE
REGISTER ADDRESS
DCP/WCR ADDRESS
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A1 A0 I3 I2 I1 I0 RB RA P1 P0 REGISTER DCP/WCR ADDRESS ADDRESS D7 D6 D5 D4 D3 D2 D1 D0
DEVICE ID
INTERNAL ADDRESS
INSTRUCTION OPCODE
DATA FOR WCR[7:0] OR DR[7:0]
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A1 A0 I3 I2 I1 I0 RB RA P1 P0 REGISTER DCP/WCR ADDRESS ADDRESS
X
X
X
X
X
X
X
X
DON'T CARE
DEVICE ID
INTERNAL ADDRESS
INSTRUCTION OPCODE
S0 D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] OR DATA REGISTER BIT [7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
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X9251
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A1 A0
1 I3
0 I2
1 I1
1 I0 RB RA P1 P0
0
0
0
0
0
0
0 WIP STATUS BIT
DEVICE ID
INTERNAL ADDRESS
INSTRUCTION OPCODE
REGISTER POT/WCR ADDRESS ADDRESS
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A1 A0 I2 I3 I1 I0 RB RA P1 P0 REGISTER POT/WCR ADDRESS ADDRESS I N C 1 I N C 2 I N C n D E C 1 D E C n
DEVICE ID
INTERNAL ADDRESS
INSTRUCTION OPCODE
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
tWRID SCK
SI
RW INC/DEC CMD ISSUED
VOLTAGE OUT
FIGURE 7. INCREMENT/DECREMENT TIMING SPEC
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X9251 Instruction Format
Read Wiper Counter Register (WCR)
Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Wiper Position (Sent by X9251 on SO) WWWWWWWW CCCCCCCC RRRRRRRR 76543210
CS Falling Edge
0
1
0
1
0
0
A1
A0
1
0
0
1
0
0
0
0
CS Rising Edge
Write Wiper Counter Register (WCR)
Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Data Byte (Sent by Host on SI) WWWWWWWW CCCCCCCC RRRRRRRR 76543210
CS Falling Edge
0
1
0
1
0
0
A1
A0
1
0
1
0
0
0
0
0
CS Rising Edge
Read Data Register (DR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 1 Instruction Opcode 0 1 1 DR and WCR Addresses RB RA P1 P0 D 7 Data Byte (Sent by X9271 on SO) D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS Rising Edge
Write Data Register (DR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 Instruction Opcode 1 1 0 0 DR and WCR Addresses RB RA P1 P0 Data Byte (Sent by Host on SI) DDDDDDDD 76543210 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS Falling Edge NOTES: 1. "A1 ~ A0": stands for the device addresses sent by the master. 2. WPx refers to wiper position data in the Counter Register 3. "I": stands for the increment operation, SI held HIGH during active SCK phase (high). 4. "D": stands for the decrement operation, SI held LOW during active SCK phase (high). Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 0 Instruction Opcode 0 0 1 RB DR Addresses RA 0 0 CS Rising Edge
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X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 1 Instruction Opcode 0 0 0 DR Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 1 Instruction Opcode 1 1 0 DR and WCR Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 1 Instruction Opcode 1 0 1 DR and WCR Addresses RB RA 0 0 CS Rising Edge
Increment/Decrement Wiper Counter Register (WCR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 0 Instruction Opcode 0 1 0 X WCR Addresses X 0 0 I/D Increment/Decrement (Sent by Master on SI) I/D . . . . I/D I/D CS Rising Edge
Read Status Register (SR)
CS Falling Edge NOTES: 1. "A1 ~ A0": stands for the device addresses sent by the master. 2. WPx refers to wiper position data in the Counter Register 3. "I": stands for the increment operation, SI held HIGH during active SCK phase (high). 4. "D": stands for the decrement operation, SI held LOW during active SCK phase (high). Device Type Identifier 0 1 0 1 0 Device Addresses 0 A1 A0 0 Instruction Opcode 1 0 1 0 WCR Addresses 0 0 1 0 0 Data Byte (Sent by X9251 on SO) 0 0 0 0 0 WIP CS Rising Edge
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X9251
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SCK, CS, SI, SO, WP, HOLD, VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0C to +70C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) Limits (Note 4) X9251. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10% X9251-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS SYMBOL RTOTAL RTOTAL RW PARAMETER End to End Resistance End to End Resistance End to End Resistance Tolerance Wiper Resistance IW = V(VCC) RTOTAL V(VCC) RTOTAL @ VCC = 3V 220 @ VCC = 5V VSS -120 0.4 Rw(n)(actual) - Rw(n)(expected) (Note 5) Rw(n + 1) - [Rw(n) + MI] (Note 5) (Note 6) (Note 6) See Macro model, (Note 6) -1 -0.6 300 20 10/10/25 +1 +0.6 VCC V dBV/Hz % MI (Note 3) MI (Note 3) ppm/C ppm/C pF TEST CONDITIONS T version U version MIN TYP 100 50 20 300 MAX UNITS k k %
IW = VTERM Voltage on any RH or RL Pin Noise (Note 6) Resolution Absolute Linearity (Note 1) Relative Linearity (Note 2) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW NOTES: Potentiometer Capacitances
VSS = 0V Ref: 1V
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/255 or (RH - RL)/255, single pot 4. During power up VCC > VH, VL, and VW. 5. n = 0, 1, 2, ...,255; m = 0, 1, 2, ..., 254.
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X9251
DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS SYMBOL ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH PARAMETER VCC supply current (active) VCC supply current (non-volatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage IOL = 3mA IOH = -1mA, VCC +3V IOH = -0.4mA, VCC +3V VCC - 0.8 VCC - 0.4 TEST CONDITIONS fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 VCC x 0.3 0.4 1 MIN. TYP MAX 400 5 3 10 10 UNITS A mA A A A V V V V V
Endurance and Data Retention
PARAMETER Minimum endurance Data retention MIN 100,000 100 UNITS Data changes per bit per register years
Capacitance
SYMBOL CIN/OUT (Note 6) Input/Output capacitance (SI) COUT (Note 6) CIN (Note 6) Output capacitance (SO) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) TEST TEST CONDITIONS VOUT = 0V VOUT = 0V VIN = 0V TYP 8 8 6 UNITS pF pF pF
Power-Up Timing
SYMBOL tr VCC (Note 6) tPUR (Note 7) tPUW (Note 7) VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation PARAMETER MIN 0.2 1 50 MAX UNITS V/ms ms ms
A.C. Test Conditions Input Pulse Levels
Input rise and fall times Input and output timing level NOTES: 6. This parameter is not 100% tested 7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
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FN8166.5 April 13, 2007
X9251 Equivalent A.C. Load Circuit
VCC 2k RH SO pin 2k 10pF 10pF RW CL CW 25pF CL 10pF SPICE Macromodel RTOTAL RL
AC TIMING
SYMBOL fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO (Note 6) tFO (Note 6) tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SPI clock frequency SPI clock cycle rime SPI clock high rime SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200 PARAMETER MIN MAX 2 UNITS MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
High-Voltage Write Cycle Timing
SYMBOL tWR PARAMETER High-voltage write cycle time (store instructions) TYP 5 MAX 10 UNITS ms
XDCP Timing
SYMBOL tWRPO (Note 6) tWRL (Note 6) PARAMETER Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) MIN 5 5 MAX 10 10 UNITS s s
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FN8166.5 April 13, 2007
X9251 Symbol Table
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SO
HIGH IMPEDANCE
Output Timing
CS
SCK tV SO MSB tHO
... tDIS ... LSB
SI
ADDR
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FN8166.5 April 13, 2007
X9251
Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ...
XDCP Timing (for All Load Instructions)
CS
SCK
... tWRL ... LSB
SI
MSB
VWx
SO
HIGH IMPEDANCE
Write Protect and Device Address Pins Timing
CS tWPASU WP A0 A1
(ANY INSTRUCTION) tWPAH
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FN8166.5 April 13, 2007
X9251 Applications information
Basic Configurations of Electronic Potentiometers
VR +VR
RW
I Three terminal Potentiometer; Variable voltage divider
Two terminal Variable Resistor; Variable current
Application Circuits
NON INVERTING AMPLIFIER VS + - VO VIN 317 R1 R2 R1 Iadj R2 VO (REG) VOLTAGE REGULATOR
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT R1 VS 100k - + TL072 10k 10k +12V 10k -12V VO R2
COMPARATOR WITH HYSTERESIS
VS
- +
VO
VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min)
} R1
} R2
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X9251
Application Circuits (continued)
ATTENUATOR C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10k R1 R2 - + VO VS R R2 + - VO FILTER
VO = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
INVERTING AMPLIFIER R1 R2
EQUIVALENT L-R CIRCUIT
}
VS
}
- +
C1 VO VS
R2 + -
VO = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
FUNCTION GENERATOR C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
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FN8166.5 April 13, 2007
X9251 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8 Rev. 1 4/06
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0 8 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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FN8166.5 April 13, 2007
X9251 Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A A1 A2 b c D E E1 e
H
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
E
E1
1 B TOP VIEW
(N/2)
0.20 C B A 2X N/2 LEAD TIPS
C SEATING PLANE
e
0.05
L L1 NOTES:
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8166.5 April 13, 2007

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